`ifndef LILYRISCV_TOP_V
`define LILYRISCV_TOP_V


`include "../core/defines.v"

module LilyRiscv_top(
	input  wire 		  clk	,
	input  wire 		  rstn     		
);

// LilyRiscv to rom 
wire[`InstAddrWidth - 1 : 0] LilyRiscv_inst_addr_o;

//rom to LilyRiscv
wire[`InstWidth - 1 : 0] rom_inst_o;

LilyRiscv u_LilyRiscv(
	.clk  			(clk  					), 
	.rstn 			(rstn					),
	.inst_i			(rom_inst_o				),
	.inst_addr_o	(LilyRiscv_inst_addr_o	)
);

rom u_rom(
	.inst_addr_i	(LilyRiscv_inst_addr_o	),
	.inst_o         (rom_inst_o				)
);


endmodule


`endif // LILYRISCV_TOP_V